A new software combines connectivity, scalability and data-driven artificial intelligence (AI) capabilities to push the boundaries of the IC verification process and make chip design teams more productive. Questa One aims to address the verification productivity gap for large, complex designs spanning IP to IC to systems.
The steadily increasing complexity of 3DICs, chiplet-based designs, and software-defined architectures is further compounded by a critical talent shortage and growing demands for enhanced security and lower power consumption. “Questa One uses new technical advances to deliver the fastest functional, fault, and formal verification engines available,” said Abhi Kolpekwar, VP and GM of digital verification technologies at Siemens EDA.
Figure 1 Questa One strives to redefine IC verification from a reactive process into an intelligent, self-optimizing system. Source: Siemens EDA
A recent Wilson Research Group survey suggests that one in seven IC projects achieves first-time silicon success. Chris Giles, director of product management for static and formal at Siemens EDA, calls this a jaw-dropping and staggering drop. “Our approach is to enable engineers to do more with less, with not just faster engines but also faster engineers with fewer workloads,” he said.
Figure 2 Here is a view of the decline in first-time silicon success and the increase in FPGA bugs. Source: Wilson Research Group
Giles spoke with EDN to explain the technology fundamentals of this new verification tool.
Quest One’s three tenets
Giles said that Questa One has been developed around three core principles:
- Scalable verification: It allows engineers to speed verification closure. Giles noted that the semiconductor industry is struggling to tackle large designs. “That’s why we see a decline in first-time silicon success,” he added. “Chip designs are getting so large that it’s difficult to verify them in one piece.” Questa One verification aims to allow engineers to work on large chip designs.
- Data-driven verification: It leverages data for AI-powered analytics to bring new insights and to improve verification productivity. “It collects datasets that allow verification tools to either make recommendations or directly decide what to do next and do it productively,” said Giles.
- Connected verification: Questa One connects EDA tools and verification IP to form a cohesive ecosystem for robust verification, validation, and test operations. In other words, it uses a broad set of technologies and analyses to provide insights and raw verification power.
Figure 3: Questa One offerings are shown with three main value propositions summed up at the bottom. Source: Siemens EDA
Quest One’s four components
Questa One has the following focus areas:
- Questa One simulator: This simulator engine is built from the ground up. It performs functional and fault simulation for RTL, GLS, and DFT applications with parallel processing and profiling add-ons.
- Questa One SFV: The stimulus-free verification (SFV) solution delivers user productivity through synergistic combinations of static and formal analyses, AI, automation, and parallelization. “The current static and formal technology is very fragmented, challenging high productivity,” Giles said. “SFV integrates static and formal analyses, AI, and parallelization to address this challenge.”
- Questa One verification IQ: It’s a coverage solution that utilizes generative, analytic, and prescriptive AI to drive verification closure faster with fewer workloads. “It features an intelligent interface that provides insight into the entire verification ecosystem,” Giles added.
- Questa One Avery VIP: The solution, based on Avery’s high-quality VIP and high-coverage compliance test suites (CTS), offers protocol-aware debug and coverage analytics to help increase productivity. It supports 3DIC and chiplet verification from IP to system-on-chip (SoC) design.
Figure 4 Four main components of Questa One include a simulator, a static and formal verification solution, a verification intelligence coverage analysis solution, and an Avery identifier. Siemens EDA
Questa One in works
Semiconductor IP supplier Rambus acknowledged an improved verification experience in managing data center workloads like generative AI while implementing IPs for PCIe, CXL, and HBM interfaces. Rambus particularly mentioned Questa One’s simulation, static and formal analysis, and verification IP technologies.
Then there is Arm, which used Questa One simulator to reduce regression time in its latest AArch64 architecture. “The Questa One verification solution has improved our verification productivity across traditional on-premises and cloud deployments,” said Karima Dridi, head of productivity engineering at Arm.
MediaTek, another early user of Questa One, has utilized its formal verification and simulation technologies. “Questa One Property Assist utilizes generative AI to save us weeks of engineering time, and Questa One Regression Navigator predicts which simulation tests are most likely to fail, runs them first, and saves days of regression and debugging time,” said Chienlin Huang, senior technical manager of Connectivity Technology Department at MediaTek.
Questa One claims to yield step-function gains in smart regression, smart analysis, smart engine, and smart debug domains. Design testimonials from Arm, MediaTek, and Rambus are a good start.
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