Like any successful system-on-chip (SoC) effort, a multi-die system-in-package (SiP) project must start with a sound system design. But then what? Are the steps in the SiP design flow different from the stages in an SoC design? What is necessary to ensure that a 2.5D or 3D SiP will be functionally correct, within the power, performance, and cost specifications, and that it will be manufacturable?
The easiest way to answer these questions is to describe the multi-die design process we have developed at Faraday through our participation in SiP designs with our clients.
Co-design from the start
Ideally, the SiP specialists will be involved in the design from the early stages. Even when the design is just a block-level sketch on a napkin, it’s not too early to begin discussing how the IP blocks will be distributed among the dies, and what the implications will be for the completed SiP (Figure 1).
Figure 1 Collaboration on a SiP design can begin with the customer’s selection of chiplets and continue through to a production-ready design. Source: Faraday Technology Corp.
A 2.5D or 3D design adds one or two additional levels to the interconnect hierarchy between the fast, efficient, and dense on-die routing and the slow, power-hungry, and sparse board-level routing. First, advanced packaging provides a silicon interposer for interconnecting the dies.
This level of interconnect is dense, although far less dense than the lower metal layers on a die, and it’s relatively energy-efficient, low-latency, and high-bandwidth, albeit not as good as on-die metal. Stacking dies—going 3D—adds another level to the hierarchy: direct connections between dies, through-silicon vias, and microbumps or hybrid bonding. This level is better than interposer connections, but still not equal to on-die connections.
The challenge in partitioning the multi-die design is that the limitations of each level of interconnect will impose themselves on whatever signals are being routed through that level. Thus, choosing what signals to carry and where will they ultimately impact system power, performance, and area. Therefore, partitioning is a key decision in this process: which IP blocks to put on which dies.
Partitioning will determine which signal paths must be routed on which levels of the routing hierarchy. Thus, partitioning decisions will influence the ease, difficulty, or impossibility of routing and timing closure on each level. If critical signals are placed on an interconnect with insufficient bandwidth or excessive latency to meet requirements, they will impact system performance.
Additionally, they will affect system power, as interconnect power consumption is not inconsequential at the system level. For these reasons, the earlier the SiP-design experts engage with the system designers, the better the resulting design quality is likely to be.
Chip and SiP
There are two distinct cases to consider here. In some SiP designs, all dies that will go into the SiP are already designed. The SiP team will then decide on die placement and, possibly, the order of dies in stacks, and will route the connections between dies. However, the partitioning of functions among the dies and the locations of individual pads on each die have already been fixed. This significantly reduces the SiP design planning problem and limits the SiP designers’ freedom.
In contrast, in some projects, one or more dies are designed specifically for the SiP. One of these new dies will often be an SoC, carrying much of the system functionality and serving as the hub for connections within the SiP. In these cases, much more optimization is possible if the die design and SiP teams work together. At the very least, the die and interposer designers can cooperate on the die pad location to ease the interposer layout.
Deeper cooperation can include optimizing the die floorplan to get the pads for critical interconnect buses in the best place to minimize interconnect length and congestion. Early cooperation may influence choices of protocols and transceivers for die-to-die connections or even reconsider the partitioning.
This added freedom is valuable. The relatively long latency, limited bandwidth, and higher power consumption of interposer and package-substrate interconnect can dominate SiP performance. Therefore, minor adjustments to a die layout that allow for significant improvements in SiP routing can result in substantial gains in system-level quality of results.
Interposer and package
The result of all this planning and co-design is a list of the exact location of each pad on each die and each ball on the package substrate, together with a routing list indicating what must connect to what. An additional vital dataset contains the signal-integrity and power-integrity requirements for each connection.
These latter specifications may come from interface standards such as Universal Chiplet Interconnect Express (UCIe), Bunch of Wires (BoW), or the High-Bandwidth Memory (HBM) channel specifications. Or they may be dictated by specific pin requirements on the dies.
Now, the 2.5D/3D team must design an interposer and package substrate that satisfies the connection, signal, and power-integrity requirements. The design should also minimize overall SiP cost and ensure manufacturability. Needless to say, this is an over-constrained optimization problem—it requires excellent tools and deep design experience to get the best result.
SiP analyses
Successful routing is not the end of this story. Before the SiP design can be released, each trace must be subjected to signal-integrity or power-integrity analysis using special analysis tools, sometimes at the detailed level of multiphysics tools. The SiP design team should provide the system designers with the SiP’s thermal and electrical characteristics for complete thermal analysis. Ideally based on actual circuit activity with production software, this analysis is often vital to ensuring the SiP’s reliability in its intended environment.
This design flow has proven successful at Faraday, emphasizing early engagement among system designers, die design teams, and SiP designers. The latter group must possess the skills and experience to recognize potential issues early, before there is sufficient data for complete analysis, when a partitioning choice, die placement, or pad location may cause trouble downstream.
The SiP team must have the skills and tools to design, optimize, and analyze the interposer and package substrate. As important as this is, the organization must have close relationships with foundry, assembly, and test partners to ensure the SiP will be manufacturable in its intended supply chain (Figure 2).
Figure 2 Close collaboration between design teams, silicon foundries, and OSAT partners is essential for the successful production of a multi-die device. Source: Faraday Technology Corp.
To return to our original question: yes, additional steps, skills, and relationships are necessary to ensure the success of an SiP. These needs make choosing a design partner one of the most critical decisions the management will make on a SiP project.
Next, close cooperation between the design teams, the silicon foundry, and the OSAT partners is necessary to produce a successful multi-die device.
Wang-Jin Chen leads Faraday’s Design Development Methodology team, which focuses on methodology, design flow, verification, and sign-off for advanced package design.
Related Content
- A systems approach delivers SiP design
- Heterogeneous integration and the evolution of IC packaging
- Overcoming the Technical Challenges of System-in-Package (SiP)
- Advanced IC Packaging: Fundamentals for the ‘More than Moore’ Era
- SiP package styles for magnetic position sensors have benefits for automotive applications
The post From system design to SiP: What’s the design flow appeared first on EDN.
